The computer industry continually strives toward higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits (“IC's”). As new generations of IC products are released, their functionality increases while the number of components needed to produce them decreases.
Semiconductor devices are constructed from a silicon (“Si”) or gallium arsenide (“GaAs”) wafer through a process that comprises a number of deposition, masking, diffusion, etching, and implanting steps. Usually, many individual devices are constructed on the same wafer. When the devices are separated into individual rectangular units, each takes the form of an IC die.
In order to interface a die with other circuitry, it is common to mount it on a leadframe or on a multichip module substrate that is surrounded by a number of lead fingers. Each die has bonding pads that are then individually connected in a wire-bonding operation to the leadframe's lead fingers using extremely fine gold (“Au”) or aluminum (“Al”) wires. The assemblies are then packaged by individually encapsulating them in molded plastic or ceramic bodies.
IC packaging technology has shown an increase in semiconductor chip density (the number of chips mounted on a single circuit board or substrate) that parallels the reduction in the number of components that are needed for a circuit. This results in packaging designs that are more compact, in form factors (the physical size and shape of a device) that are more compact, and in a significant increase in overall IC density. However, IC density continues to be limited by several factors.
One factor that limits IC density is the space (or “real estate”) available for mounting individual dies on a substrate. Another limiting factor is the increasing need for higher and higher heat dissipation due not only to the higher density IC integration levels, but also due to the ever-increasing operating frequencies of the semiconductor devices. Still another limiting factor is the need to provide customized physical and electrical support for the differing individual needs of the semiconductor devices in such high density configurations.
To increase heat dissipation, thermally enhanced package designs, such as enhanced ball grid array (“EBGA”) packages, have been developed. Such packages are particularly directed to high-level integration devices, and utilize a heat sink to dissipate the considerable heat that is generated by the high-power semiconductor devices contained therein.
To further condense the packaging of individual devices, multichip-module (“MCM”) packages have been developed in which more than one semiconductor device can be included in the same package. Examples of thermally enhanced multifunctional ball grid array (“BGA”) packages include the MCM enhanced BGA (“MCM-EBGA”) with an attached multicavity heat spreader, and the MCM drop-in heat spreader for plastic BGA (“PBGA”) packages. These higher integration techniques provide for mixed signal packages that enable higher functionality, allowing, for example, different chip sets to be integrated into a single package to provide multifunctional performance.
In some cases, multichip devices can be fabricated faster and more cheaply than a corresponding single IC die that incorporates the same features and functions. Some MCM's consist of a printed circuit board (“PCB”) substrate onto which a set of separate IC chip components is directly attached. Other MCM's mount and attach multiple dies on a single leadframe. Following assembly, the MCM's are then encapsulated to prevent damage or contamination. Many such MCM's have greatly increased circuit density and miniaturization, improved signal propagation speed, reduced overall device size and weight, improved performance, and lowered costs—all primary goals of the computer industry.
Of importance to such complicated packaging designs are considerations of input/output lead count, heat dissipation, the differing voltage requirements of the several semiconductor devices in the packages, matching of thermal expansion and contraction between a motherboard and its attached components, costs of manufacturing, ease of integration into an automated manufacturing facility, package reliability, and easy adaptability of the package to additional packaging interfaces such as a PCB.
Unfortunately, existing multichip modules do not satisfactorily meet these requirements. For example, existing MCM-EBGA designs employ a single heat sink plane and therefore do not make different die backside electrical potentials available for the various semiconductor devices therein. Thermally enhanced PBGA designs utilize a drop-in heat spreader that accommodates high-power devices that need considerable heat dissipation but cannot support certain different die backside potentials.
Thus, despite the advantages of recent developments in semiconductor fabrication and packaging techniques, there is a continuing need for improved packaging designs, systems, and methods to enable increased semiconductor die density in multichip packages. A need particularly remains for such improved package solutions that have enhanced thermal performance while simultaneously being capable of integrating multi-chipsets that require different die backside potentials. In view of the need to increase package efficiency and capacity, reduce package thicknesses, increase package heat dissipation capabilities, and support multiple die backside potentials, it is increasingly critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.